1. Field of the Invention
The present invention relates to a circuit for erasing the leakage current of DRAM, more particularly to a circuit for erasing the short DC standby current between the bit lines and the word lines of DRAM.
2. Background of the Invention
In the manufacturing process of DRAM, a short circuit between the bit line and the word line sometimes occurs and causes a leakage current and affect the product yield.
One of the solutions for the above-mentioned problem is disclosed in U.S. Pat. No. 5,499,211, entitled “BIT-LINE PRE-CHARGE CURRENT LIMITER FOR CMOS DYNAMIC MEMORIES.” As shown in FIG. 1, a conventional circuit 10 comprises a word line 12, a pair of complementary bit lines 13, a pre-charge equalization circuit 14 and a current-limiting means 11. In prior art, in order to prevent an excess leakage current caused by the short circuit between the bit line (BL) and the word line (WL), a current-limiting means 11, such as a depletion NMOS, is added between a source of pre-charge voltage (VBLEQ) 15 and the pair of complementary bit lines 13 so as to limit the maximum leakage current when the short circuit between the bit line and the word line occurs.
Generally, the word line voltage (VWL) is 0 volt in the standby mode, such as the word line driving circuit 20 shown in FIG. 2(a). However, the bit line voltage is larger than 0 volt, so a leakage current path will be formed in the standby mode. The leakage current will flow from BLEQ, BL, and WL to the ground. FIG. 2(b) shows a timing diagram of FIG. 1 and FIG. 2(a). In other words, the conventional method cannot effectively erase the leakage current when the short circuit occurs between the bit lines and the word lines. For the current application in the product for low power DRAM, the leakage current is still too large to satisfy the market requirement.
Regarding the problems in the prior art, the present invention provides an innovative standby current erasion circuit for the DRAM to overcome the above-mentioned disadvantages.